大学英语词汇短语释义解析及例句 clock skew
释义：
clock skew 时钟歪斜；时钟脉冲相位差; 时钟偏移
例句：
We first analyze the worst-case clock skew of PD connection structures.
在这篇论文中，我们首先分析给定相差侦测器架构下最糟的时脉偏移量。
The error messages you will get from clock skew will not generally be obvious.
在时钟问题中产生的错误消息通常都不太明显。
Clock signal and clock skew become more and more important in the circuit performance.
时钟信号和时钟偏差对电路性能的影响也越来越明显。
Clock skew is in a synchronization digital integrated circuit design difficult problem.
时钟偏移是同步数字集成电路设计中的一个难题。
A yield driven clock skew scheduling algorithm is proposed in presence of process variations.
针对工艺参数变化的情况，提出一种成品率驱动的时钟偏差安排算法。
In order to avoid clock skew familiar in high-speed sequential logic circuits, buffers are placed in clock-tree.
为了避免高速时序电路中常见的时钟偏差，在时钟树中放置了缓冲器。
Then we propose an algorithm to generate an optimal PD connection structures resulting in the minimum clock skew.
接著，我们提出一个能够产生最小时脉偏移之相差侦测器架构的演算法。
In clock routing, clock signal and clock skew become more and more important for impact of the circuit performance.
在时钟布线中，时钟信号和时钟偏差对电路性能的影响越来越明显。
Knowledge of process variation is important to optimize critical path delay, minimize clock skew, and reduce crosstalk noise.
过程变化的知识对于最优化电路延时，减少时钟倾斜和降低串扰噪声很重要。
the Kerberos authentication protocol requires that the clock skew between a server and a client is no greater than 5 minutes.
Kerberos身份验证协议要求服务器和客户机之间的时钟差不大于5分钟。
This paper presents an effective approach for clock skew scheduling that can reduce the center error square and assign slacks incrementally.
本文提出了一种有效的方法时钟歪斜调度中心可以减少误差平方和增量分配的休闲裤。
After analyzing the Clock delay, the Clock Skew and the critical steady synchronizer which are difficult in the design, some settle methods are introduced.
同时就设计中常遇到的三个问题：时钟延时，时钟偏移，同步器的亚稳态性加以说明且提出了解决方法。
Serial communications based on SERDES adopt the clock_data recovery(CDR) instead of both data and clock transmitting, which solve the problem of clock skew.
基于SERDES的串行通信过程中采用时钟和数据恢复技术（CDR）代替同时传输数据和时钟，从而解决了限制数据传输速率的信号时钟偏移问题。
In this thesis, we show that how FFs are connected by PDs can also greatly influence the final clock skew due to limitations of a practical ADB and PD design.
在这篇论文中，我们提出由于实际的可调变延迟缓 冲器及相差侦测器设计上有其物理上的限制，相差侦测器连接正反器的拓墣也会影响最后的时脉偏移。
The design of asynchronous circuits is widely used in modern VLSI design, which is able to resolve the problems of power dissipation, system speed, clock skew, etc.
异步电路的设计能够解决功耗、系统速度、时钟偏移等问题，成为当前VLSI研究的热点。
A new clock skew scheduling algorithm is proposed. This algorithm generates timing constraints which can effectively promote the area optimization of logic syn thesis.
提出了一种新的时钟偏斜规划算法，该算法所生成的时序约束可以有效地促进逻辑综合工具的面积优化。
