大学英语词汇短语释义解析及例句 clock cycle


释义：

clock cycle 时钟周期

例句：


A microprocessor clock cycle in which nothing occurs.

一个处理器的时钟周期内，没有发生。



Each decoded output remains high for one full clock cycle.

每个解码输出在一个全时钟周期内保持高电平。



Accesses to local store memory can be predicted down to the clock cycle.

对本地存储内存的访问的预测可以精确到时钟周期级别上。



Its first design was very simple and all instructions were completed in one clock cycle.

它的第一个设计非常简单，所有指令都在一个时钟周期内完成。



An SPU USES vector operations itself and can thereby execute up to eight floating point instructions per clock cycle.

SPU本身使用向量操作，每个时钟周期可以执行多达8条浮点指令。



It is more efficient to design a simple instruction set that enable the execution of one instruction per clock cycle.

设计一个能够在一个时钟周期执行一条指令的简单指令系统才是更有效的。



Each set of three horizontal boxes within each processor shows how the three execution units are being used during a given clock cycle.

每个处理器内每组三个水平方框显示了在指定的时钟周期内，三个执行单位是如何被使用的。



The POWER4 microprocessor collects a group of up to five instructions per clock cycle and can complete one group of instructions per clock cycle.

POWER 4微处理器每个时钟周期收集一组指令(最多有5个)，并在每个时钟周期内完成一组指令。



Suppose that Enable is high, the counter counts up every clock cycle, and the frequency of the PWM output is the clock frequency divided by 2 count bits.

假设高信号使能，计数器每个时钟周期进行计数，PWM输出的频率为时钟频率的2次幂分频。



The POWER5 microprocessor doubles that throughput by collecting two groups of up to five instructions per clock cycle and completing two groups per clock cycle.

POWER 5微处理器使此吞吐量增加了一倍，每个时钟周期收集两组指令(每组最多有五个)，并在每个时钟周期内完成两组指令。



In this thesis we discuss such a DSP, which USES a clustered VLIW architecture and can perform multiple operations simultaneously during a single clock cycle.

本文讨论这样一款DSP，它采用分簇的VLIW体系结构，能够在单个时钟周期同时执行多个操作。



What CCK does is to apply sophisticated mathematical formulas to the DSSS codes, permitting the codes to represent a greater volume of information per clock cycle.

CCK所做的工作是把复杂的数学公式应用于DSSS代码，以允许该代码在每个时钟周期表示更多的信息。



Devadas has demonstrated that small circuits connected to the cores can calculate the allotment of bandwidth and switch the direction of the connections in a single clock cycle.

Devadas已经成功演示了一种能计算带宽分配且能在一个时钟周期内改变连接传输方向的小型电路。



Instruction 4 can be issued in the clock cycle immediately after instruction 3 because it does not require the result of instruction 3 to execute. You can visualize it like this.

指令4可以在指令3之后紧接的那个时钟周期执行，因为它不需要指令3的结果来执行。



Another unique architectural feature is the memory system which allows an instruction fetch and at the same time a data access by each individual core at every single clock cycle.

另一个独特的构架特性是内存系统，它允许一个取指，并在同一时间，每一个核可以读取数据在每一个单独的时钟周期内。



Simultaneous Multithreaded Processors improve the instruction throughput by allowing fetching and executing instructions from several running threads simultaneously in each clock cycle.

同时多线程处理器在每时钟周期从多个线程读取指令执行，极大地提高了指令吞吐率。